IEC 63378-6 ED1

Thermal standardization on semiconductor packages - Part 6: Thermal resistance and capacitance model for transient temperature prediction at junction and measurement points

General information

Current stage: 60.00 Effective date: 9 jan 2026

Next stage: PPUB Next stage date: 20 shk 2026

Originator: IEC

Owner: TC 47/SC 47D

Type: International Standard

ICS: 31.080.01

Scope

IEC 63378-6:2026 specifies a thermal resistance and capacitance model for semiconductor packages. This model is named the digital transformation using thermal resistance and capacitance (DXRC) model. It predicts transient temperature at junction and measurement points.
This document applies to semiconductor packages such as TO-252, TO-263, and HSOP. It supports single chip packages dissipated heat from single package surface.

Life cycle

NOW

IN_DEVELOPMENT
IEC 63378-6 ED1
60.00 Standard under publication
9 jan 2026