Published
Describes a high-performance backplane bus for use in microprocessor bases systems. This parallel bus supports single- and block-transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaken protocol. The bus allocation provides for multiprocessor architectures. This bus also supports inter-module interrupts for facilitating quick response to internal and external events. The mechanics of the boards and chassis are based on IEC 60297. Note: -1.This bus is similar to the VME bus. 2.For the price of this publication, please consult the ISO/IEC price-code list.
Revises
iec:proj:1000001721
PUBLISHED
IEC 60821:1991 ED2
60.60
Standard published
Dec 17, 1991
Amended by
IEC 60821:1991/AMD1:1999 ED2
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