IEC 63011-3:2018 ED1

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via

Publication date: Nov 28, 2018

General information

Current stage: 60.60 Effective date: Nov 28, 2018

Originator: IEC

Owner: TC 47/SC 47A

Type: International Standard

ICS: 31.200

Languages: English French

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Status: Published

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Scope

IEC 63011-3:2018 specifies a reference model of through-silicon via (TSV) electrical characteristics required for an interface design in three dimensional integrated circuit (3-D IC) to transmit and receive digital data and measurement conditions for resistance and capacitance to specify TSV characteristics in 3-D IC.
Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the scope of this document.

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PUBLISHED
IEC 63011-3:2018 ED1
60.60 Standard published
Nov 28, 2018

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SSH IEC 63011-3:2018

DPS

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via

60.60 Standard published

DPS/KT 7 more